Along with frequency improvements from the lengthened pipeline to allow for
microarchitectural enhancements, the Hammer processor will be initially produced using
a .13micron SOI (Silicon on Insulator) process technology. The microarchitecture is
implemented to scale well in frequency with process scaling below the .10micron level.
On the other end of the performance equation are the key features that improve the ability
of the Hammer microarchitecture to recognize a higher IPC (Instructions executed Per
Clock) than previous generation microarchitectures.