The performance-monitoring counters are supported by four MSRs: the performance event
select MSRs (PerfEvtSel0 and PerfEvtSel1) and the performance counter MSRs (PerfCtr0 and
PerfCtr1). These registers can be read from and written to using the RDMSR and WRMSR
instructions, respectively. They can be accessed using these instructions only when operating at
privilege level 0. The PerfCtr0 and PerfCtr1 MSRs can be read from any privilege level using
the RDPMC (read performance-monitoring counters) instruction.
The PerfEvtSel0, PerfEvtSel1, PerfCtr0, and PerfCtr1 MSRs and the events
listed in Table A-1 in Appendix A, Performance-Monitoring Events are
model-specific for P6 family processors. They are not guaranteed to be
available in future Intel Architecture processors.