rfs
05/12/2008, 18h44
Looking at the source code for the tests done, I notice that they interleave the steps of verifying an address, followed by writing the anti-pattern to the same address, before moving on to the next address. Is this an intentional goal, or is it merely the simplest way to do the tests?
Perhaps I am naive, but in order to really stress the memory interface, would you not want to use bursts (rather than individual transfers)? This would mean reading a whole block of data, before writing the anti-pattern. Would this defeat the ability to detect memory errors? Or perhaps it is just too difficult to implement this portably enough to work on a wide range of CPU & northbridge combinations?
Thanks for your insights!
Perhaps I am naive, but in order to really stress the memory interface, would you not want to use bursts (rather than individual transfers)? This would mean reading a whole block of data, before writing the anti-pattern. Would this defeat the ability to detect memory errors? Or perhaps it is just too difficult to implement this portably enough to work on a wide range of CPU & northbridge combinations?
Thanks for your insights!